1. Field of the Invention
The invention relates to improvements in a read-only memory. In particular the invention relates to a VLSI memory array precharge improvement, a latch circuit improvement to minimize metastability in dynamic digital circuits.
2. Description of the Prior Art
Memory Array Precharge
FIG. 19 of the parent application referenced above shows a precharged circuit whose operation is illustrated in the timing diagram of FIG. 20 of that same application. The architecture of this memory array is comprised of four blocks: (1) a Y-decoder block for the high address portion; (2) a Y-decoder block for the low address portion; (3) a memory cell block; and (4) a precharge block. The memory array is provided with a precharge voltage, VPC. Charging and discharging the bit lines are controlled by the signals, SELV, PC0, PC1 and PC2.
PC2 serves to precharge the bit line from the memory array itself. PC2 provides a bit charge which charges only selected bit lines which are connected to a sense amplifier to a certain precharge level.
PC1 is then coupled in common to the gates of a plurality of precharged transistors which are coupled in series with each virtual ground line and bit line within the memory cell block. PC1 is therefore used as a blanket precharge and charges all bit lines and source side select lines to a predetermined charge level.
PC0 is coupled in common to the gates of the precharged transistors within the memory array, which transistors are coupled between adjacent bit lines in the array similar to that as shown in FIG. 18 of the parent application incorporated above. The precharged transistors short each of the bit lines together to allow a precharge to be coupled through the transistors to all the bit lines within the memory block. PC0 is therefore a bank precharge signal. PC0 charges all the bit lines in a selected bank which are precharged and shorted together so that the previous charge from any previously selected memory cell access within the block is eliminated. The bit lines are precharged equally with a predetermined precharged level.
The control signal, SELV, is a select virtual ground command which pulls the source side of a selected memory cell bit to ground level.
The address lines YDLi and YDUi, corresponding to the lower and upper address bits, are typically low during precharge. Only one address line YDLi and one address line YDUi are driven high during the evaluate or read cycle.
Metastable Latch Circuit
In memory circuits or other dynamic digital circuits, latches are used to accepts various signals, such as addresses to implement the read or write signal with proper timing. In some cases the latch is likely to fall into a metastable state which can cause a dynamic ROM, for example, not to accept any new address transitions or to cause a dynamic ROM to output incorrect data. To avoid latch contentions design modifications of the latches are used which introduce time delays. These delays then must be accommodated by the logic design of the architecture. What is needed is a latch design which is not susceptible to failure in latch contentions and which is transparent insofar as the timing of the circuitry is concerned.
Data Multiplexing in Very Large Scale Integrated Memories with Optimum Operating Speed
FIG. 6 illustrates a typical prior art, read-only memory in which the memory core is divided into a left core half 62 and right core half 64. Each core half 62 and 64 produces eight bits or one byte of the output word. The bytes are multiplexed through a multiplexer 66 whose output is coupled to a sense amplifier 68. The output of the sense amplifier in turn is provided as an input to a driver circuit 70 whose output is connected to the output pads 72 to communicate the left and right bytes in sequence to the outside environment, typically a bus.
The disadvantages of the prior art approach as shown in FIG. 6 is that both halves of the memory core 62 and 64 must be powered up and coupled through multiplexer 66 to sense amplifier 68. The chip layout for this coupling is geometrically complex and generally introduces opportunities for undesirable parasitic effects. The generation of internal noise voltages within the two memory core halves 62 and 64 also creates an inherent limitation to circuit speed.
Therefore, what is needed is a memory organization and supporting sense amplifier and multiplexer circuitry which overcomes these defects.
A One Shot Pulse Generator for a Very Large Scale Integrated Memory Precharge Time Control
The parent application upon which this depends shows the advantages of dynamic precharge and blanket precharge of all the core elements within a very large scale integrated read only memory. A typical approach to generate the timing signals is depicted in FIG. 12. The logic circuitry of FIG. 12 determines when to switch the precharge clock PC0 to a logical zero as measured from the start of the memory cycle by means of several cascaded logic gates. The propagation delay time through the cascaded gates determines when PC0 will be switched low. The prior art design of FIG. 12 is, however, ill adapted for a CMOS circuitry and more generally is difficult to provide an optimum precharge time for the ROM core because timing control, which is subject to process variations, temperature and supply voltage variations, is very approximate.
Therefore, what is needed is a circuit which will overcome each of the defects of a memory precharge timing circuit as exemplified by the prior art of FIG. 12.
CMOS Trigger Circuit
A typical NMOS ROM trigger circuit is shown in FIG. 24 of the parent application and uses two inputs and has one output which switches or triggers from a logical zero to a logical one when the input ramps downwardly relatively slowly to about 0.2 volts less than the second input.
What is needed is a CMOS sense circuit which includes an automatic quick power-down to zero after the output switches have switched to a logical one. Further, also what is need is a trigger circuit which can trigger on less than 0.2 voltage difference in the inputs.
One-shot Pulse Generator for VLSI Memory Timing Control
FIG. 21 in the copending parent application shows NMOS ROM timing control circuit which determines by means of a word dummy line and associated control logic gates the time at which to switch the precharge clock, PC0, to 0 as measured from the start of a memory cycle. The precharge clock, PC0, is not switched to 0 until the output of the dummy word line delay circuit, OWUP, has switched low.
This design is not compatible with CMOS processing and requires the use of two dummy word lines. The prior art circuit also has no means for powering-down when inactive and therefore continues to use power even when inactive. Therefore, what is needed is a timing control circuit which is not subject to each of these limitations of the prior art.
RC Delay Circuit To Block Address Transition Detection
Means have previously been described in the parent copending application for blocking address transition detection at the time that output buffers are changing through the use of a timing circuit whose output is SURG. However, the circuitry there described in connection with FIG. 35 of the copending parent application is not adapted to a CMOS process, and is based upon logic gates and inherent delays in those gates. These delays are subject to variations in process parameters and operating voltages. Therefore, what is needed is a delay circuit which can block address transition detection in a controlled manner without being subject to these process and operating voltage variations.
CMOS Sense Amplifier/Latch Circuit for a Single Data Input Signal
The NMOS read-only memory sense amplifier described in the parent application upon which this application copends used four inputs and had a latch function. This design is ill adapted to the CMOS environment. Further, improved data latch operation would be desired to provide some type of means for increasing immunity to bit line noise. Still further, it would be advantageous to power-down the sense amplifier to zero power dissipation while retaining the latched data.
A Low Noise X Decoder Circuit for Use in a Semiconductor Memory
X decoders used in addressing memories provide a selection function by which a particular polysilicon or polycide word line is moved from a lower, off-voltage state to a higher on-voltage state with all word lines held low. The particular word line which is selected is determined according to the voltages or signals on the multiple address input lines. Each unique combination or configuration of addresses selects one unique word line. Conventional read-only memories, random access memories or programmable read-only memories have X decoders which are designed using stages of logic gates, NAND and NOR gates followed by buffers. In the case of NMOS technology, voltage pumps are used to insure full scale voltage expressions.
This prior art approach is particularly susceptible to noise of a type which the present invention suppresses. Noise in the X decoder is a product of the decoder design and becomes apparent in very large memories which are now beginning to be built.
Therefore, what is needed is a means for suppressing the unique type of electrical noise which occurs in these types of X decoders.
Improved Time Constant Generation Circuit
The accurate control of circuits used in semiconductor memories is based upon the availability of a stable time reference. Typically, for the sake of simplicity and cost, an RC time circuit is provided using integrated resistive and capacitive elements. Typical prior an approaches for creating time delays have used: (1) pair delay integrated circuit logic elements; (2) RC time delay using integrated elements; (3) RC time delays using hand-selected resistive and/or capacitive external element; and (4) crystal based tuning elements using external crystals and connectors. Each of these supposes varying cost and accuracy proportionately with the first approach being the least costly and accurate and the last being the most costly and accurate.
What is needed is a means for utilizing low cost timing approaches such as described in the first and second options above, but to do so with accurate results not typical of those prior art approaches.
Memory Circuit Yield Generator and Timing Adjustor
The use of a dummy decoder in a semiconductor memory to obtain an optimum sense time and to provide adjustment for device leakage, capacitance loading, transistor characteristics and the like is well known. However, no means has been devised to provide for higher production yields in such dummy decoders when the circuit being produced had a slower speed requirement.